A. Field of the Invention
This invention generally relates to circuit testing, and, more particularly, to methods and apparatus for synchronizing asynchronous test structures and eliminating clock skew considerations.
B. Description of the Related Art
Advances in technology, such as complex integrated circuits (ICs) that use surface mount technology, have made traditional in-circuit testing methods extremely difficult. One approach for testing complex ICs is by using the Joint Test Action Group (JTAG) standard, which was developed by an international group of electronic manufacturers. This standard has been adopted by the Institute of Electrical and Electronic Engineers (IEEE) as IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture (the "IEEE standard"), the contents of which are hereby incorporated by reference.
The JTAG standard is frequently used for boundary scan testing, which allows testing based on an IC's inputs and outputs. The JTAG standard, however, may also be used to test the core logic of an IC. Typically, this is done by serially connecting the core logic's storage elements to form a scan path. Using a JTAG controller in conjunction with this scan path, one can input or output data contained in the storage elements in a fashion similar to that of a shift register. These procedures are frequently called scanning information into or out of the storage elements.
One problem with using the JTAG standard for testing core logic, however, is that the JTAG standard is invasive. Because data is entered or outputted serially from one storage element to another, the data originally contained in those storage elements is altered in the process.
One approach for overcoming this problem is to employ a series of secondary storage elements that duplicate, or take a "snapshot" of, the information in the core logic's primary storage elements. These secondary storage elements may then be connected together to form a separate, independently-addressable scan path (the secondary scan path). The information contained in the primary storage elements can then be scanned out via the secondary scan path without altering the primary storage elements. This secondary scan system allows an IC to remain operational while a snapshot of the core logic information is scanned out.
For this system to comply with the JTAG standard, the secondary storage elements in the secondary scan path must be driven based on an external clock signal, referred herein as TCK. This creates two significant problems. First, the core logic's primary storage elements are driven by a system clock that is not synchronized with the TCK and that typically operates at a much higher speed than does the TCK. If the two clock signals are not synchronized, the secondary scan system will not work and there is a chance that the IC may be damaged. Second, the TCK signal is not skew-controlled, which could result in races and metastability between the secondary storage elements. Although it may be possible to create a skew-controlled clock grid for the TCK signal, doing so would be difficult and expensive.
There exists, therefore, a need to synchronize an external clock signal (such as the TCK signal) used to drive secondary storage elements with the system clock signal used by an IC's primary storage elements, and to control skewing of the external clock signal.